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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 8-bit, 4-channel data acquisition system ad8401 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram v out dgnd ag dac ag adc data i/o (8 bits) m u x t/h 8-bit adc 1.25 ref 8-bit dac rs int busy st dac reg adc reg control logic a0 a1 v dd (+5.0v) rd wr clk cs ad8401 v a in v b in v c in v d in features 2 m s adc with t/h 4-channel mux ad899 compatible +5 volt operation on-chip reference 4 m s voltage output dac fast bus access time75 ns applications servo controls digitally controlled calibration process control equipment general description the ad8401 is a complete data acquisition and control system containing adc, dac, 4-channel mux, and internal voltage reference. built using cbcmos, this monolithic circuit offers the user a complete system with very high package density and reliability. the converter is a successive approximation adc with t/h, and is capable of operating with conversion times as short as 2 m s. analog input bandwidth is 200 khz, and dac output volt- age settling time is less than 4 m s, making the ad8401 capable of controlling servo loops with speed and precision. the 8-bit data interface provides both read and write operation for parallel bus interfaces to microcontrollers and dsp proces- sors. an external 5 mhz clock sets the 2 m s conversion rate. slower clocks reduce the conversion time and the internal power dissipation. the standard control lines: reset, busy, interrupt, read and write complete the handshaking signals for micro- processor communication. a start trigger st input allows pre- cise sampling intervals in synchronous sampling applications. the input multiplexer addressing is designed for direct interface to the ad899 hard-disk drive, read-channel device with no extra hardware or special software. analog input range levels are like- wise compatible with the ad899. the ad8401 is designed to operate from a single +5 volt sup- ply, which will give an adc input range of 0 v to 3.0 v, and dac output range of 0 v to 2.5 v. the ad8401 is offered in the soic-28 surface mount package, and is guaranteed to operate over the extended industrial tem- perature range of C40 c to +85 c.
parameter symbol conditions min typ max units static performance resolution n 8 bits total unadjusted error tue 3 lsb relative accuracy inl C1 +1 lsb differential nonlinearity dnl C1 +1 lsb offset error v ose t a = +25 c C4 +4 lsb t a = full temp range C6 +6 lsb full-scale error a e t a = +25 c C4 +4 lsb t a = full temp range C6 +6 lsb d full-scale/ d v dd t a = +25 c 1 lsb dynamic performance signal-to-noise ratio snr 44 db total harmonic distortion thd 48 db intermodulation distortion imd 60 db frequency response 0 to 200 khz 0.1 db track/hold acquisition time t aq 200 ns analog inputs (applies to inputs a, b. c, d) unipolar input range v in 03v input current i in C500 +500 m a input capacitance c in 10 pf logic inputs clock input current low i ckl v in = 0 v 1.6 ma clock input current high i ckh v in = v dd 40 m a input leakage current i l cs , rd , rs , st 10 m a logic outputs (applies to outputs db0Cdb7, int , busy ) logic output low voltage v ol i ol = 1.6 ma 0.4 v logic output high voltage v oh i oh = 200 m a 4.0 v output leakage current i oz cs = 1 (except int & busy )10 m a output capacitance c oz cs = 1 (except int & busy )10pf conversion time t c external clock 2 m s specifications subject to change without notice. rev. 0 C2C ad8401Cspecifications adc electrical characteristics a1 a0 input selected 00v in a 01v in b 10v in c 11v in d table i. multiplexer address input decode (@ v dd = +5.0 v 6 5%, ag dac = ag adc = 0.0 v; f clk = 5 mhz; C40 8 c t a +85 8 c, unless otherwise noted)
dac electrical characteristics parameter symbol conditions min typ max units static performance resolution n 8 bits total unadjusted error tue 2 lsb relative accuracy inl C1 +1 lsb differential nonlinearity dnl C1 +1 lsb offset error v ose t a = +25 c C2 +2 lsb t a = full temp range C2.5 +2.5 lsb full-scale error a e t a = +25 c C3 +3 lsb t a = full temp range C4 +4 lsb d full-scale/ d v dd t a = +25 c C0.5 +0.5 lsb load regulation at full-scale C0.2 +0.2 lsb dynamic performance signal-to-noise ratio snr 44 db total harmonic distortion thd 48 db analog output output voltage range ovr 0 +2.5 v logic inputs (applies to db0Cdb7, cs , wr , rd , rs ) logic input low voltage v il 0.8 v logic input high voltage v ih 2.4 v input leakage current i l C10 10 m a input capacitance c il 10 pf ac characteristics voltage output settling time t s to 1/2 lsb of final value 2 4 m s positive full-scale change t pos 10% to 90% 1 2 m s negative full-scale change t neg 90% to 10% 2 4 m s dac glitch impulse 15 nv s digital feedthrough 1 nv s v in to v out isolation f = 50 khz 60 db power requirements positive supply current i dd no load 13 ma specifications subject to change without notice. (@ v dd = +5.0 v 6 5%, ag dac = ag adc = 0.0 v; r l = 2 k v , c l = 100 pf to ag dac ; C40 8 c t a +85 8 c, unless otherwise noted) ad8401 C3C rev. 0
ad8401 C4C rev. 0 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8401 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. timing electrical specifications (@ v dd = +5.0 v 6 5%, ag dac = ag adc = 0.0 v; f clk = 5 mhz; C40 8 c t a +85 8 c, unless otherwise noted) parameters 1, 2, 3 symbol condition min typ max units dac timing (see figure 8 timing diagram) wr pulse width t 1 50 ns cs to wr setup time t 2 0ns cs to wr hold time t 3 0ns data setup time t 4 60 ns data hold time t 5 0ns adc timing (see figures 6 and 7 timing diagrams) st pulse width t 6 40 ns st to busy delay t 7 110 ns busy to int delay t 8 30 ns busy to cs delay t 9 0ns cs to rd setup time t 10 0ns rd pulse width 4 t 11 75 ns cs to rd hold time t 12 0ns data access after rd t 13 c l = 20 pf 10 75 ns data access after rd t 13 c l = 100 pf 10 135 ns bus relinquish after rd t 14 10 70 ns rd to int delay t 15 85 ns rd to busy delay t 16 110 ns data valid after busy t 17 c l = 20 pf 90 ns data valid after busy t 17 c l = 100 pf 135 ns notes 1 all input control signals are specified with t r = t f = 5 ns (10% to 90% of +5 v) and timed from a voltage level of 1.6 v. 2 t 13 and t 17 are measured with the load circuits of figure 1 and defined as the time required for an output to cross either 0.8 v or 2.4 v. 3 t 14 is defined as the time required for the data line to change 0.5 v when loaded with the circuit of figure 2. 4 t 15 is determined by t 13 . absolute maximum ratings* supply voltage (v dd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 v input voltages . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v output short-circuit duration . . . . . . . . . . . . . . . . indefinite package power dissipation . . . . . . . . . . . . . . (t j maxCt a )/ q ja thermal resistance q ja 28-lead soic (r) . . . . . . . . . . . . . . . . . . . . . . . . . 53 c/w storage temperature range . . . . . . . . . . . . C65 c to +150 c operating temperature range . . . . . . . . . . . . C40 c to +85 c junction temperature range (t j max) . . . . C65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package package model* range description option ad8401ar C40 c to +85 c 28-lead soic sol-28 AD8401CHIPS +25 c die *the ad8401 contains 1257 transistors. figure 1. load circuits for data access time test a. v oh to high z a. high z to v oh b. high z to v ol dgnd cl 3k w dbn dbn cl 3k w +5v dgnd dgnd 10pf 3k w dbn dbn 10pf 3k w +5v dgnd b. v ol to high z figure 2. load circuits for bus relinquish time test
ad8401 C5C rev. 0 pin descriptions pin# name description 1v dd positive supply. nominal value +5 volts. this pad requires 2 bonds for die assembly. the substrate is common with v dd . 2ag dac analog ground for the dac. there is a separate analog ground for the adc. 3v out voltage output from the dac. 4 nc no connect. 5 a1 address input that controls multiplexer. see table i for address decode. 6 reset ( rs ) active low digital input that clears the dac register to zero, setting the dac to mini- mum scale. it also asynchronously clears the int line of the adc. 7C12, 14, 15 db7 to db0 digital i/o lines. db7 (7) is the most significant bit (msb), for both the adc and the dac, and db0 (15) is the least significant bit (lsb). 13 dgnd digital ground. 16 wr rising edge triggered write input. used to load data into the dac register. 17 cs chip select. active low input 18 rd active low read input. when this input is active, adc data can be read from the part. rd going low starts the adc conversion. 19 st falling edge triggered start input. used for applications requiring precise sample tim- ing. the falling edge of st starts the conversion and sets the busy low. the st is not gated by cs . 20 busy adc active low, status output. when the adc is performing a conversion, the busy output is low. 21 int active low output. the interrupt output notifies the system that the adc has com- pleted its conversion. int goes high on the rising edge of cs or rd . it will also be forced high when reset is asserted. 22 clk external clock input pin. accepts a ttl or 5 v cmos input logic levels. 23 ag adc analog adc ground 27C24 v in a, b, c, d four analog inputs 28 a0 address input that controls multiplexer. see table i for address decode. pin configuration top view (not to scale) 1 2 3 7 8 9 10 11 12 4 5 6 13 14 28 27 26 22 21 20 19 18 17 25 24 23 16 15 ad8401ar v dd ag dac v out nc a1 db7 db6 db5 db4 db3 db2 dgnd db1 a0 v in a v in b v in c v in d ag adc clk db0 busy int st rd cs wr rs nc = no connect dice characteristics 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 die size 91 x 121 mil = 11,011 sq mil 28
ad8401 C6C rev. 0 operation the ad8401 is a complete data acquisition and control system. it contains the dac, a four channel input multiplexer, a track/ hold, an adc, as well as an internal bandgap reference. it inter- faces to the microcontroller via an 8-bit digital i/o port. d/a converter section the dac is an 8-bit voltage mode dac with an output that swings from ag dac to the 1.25 volt bandgap voltage. it uses an r-2r ladder fed by pnp current sources which allow the output to swing to ground so that the dac operates in a unipolar mode. amplifier section the dacs output is buffered by an internal high speed op amp. the op amps output range is set at 0 v to 2.5 v. the op amp has a 500 ns typical settling time to 0.2% for positive slewing signals. there are differences in settling time for nega- tive slewing signals. signals going to zero volts will settle slightly slower to ground than is seen in the positive direction. 20 w 20 w v out v dd ag dac n-ch figure 3. equivalent amplifier output stage current sinking capability is also limited near zero volts in single supply operation. figure 3 provides an equivalent amplifier out- put stage schematic. internal reference an on-chip bandgap is provided as a voltage reference to both the dac and the adc. this reference is internal to the ad8401 and is not accessible to the user. it is laser trimmed for both absolute accuracy and temperature coefficients. the refer- ence is internally buffered by a separate control amplifier for both the dac and adc to improve isolation between the converters. digital i/o the 8-bit parallel data i/o port on the ad8401 provides access to both the dac and the adc. this port is ttl/cmos com- patible with three-state outputs that are esd protected. the data format is binary. this data coding applies to both the dac and the adc. see the applications information section. adc section a fast successive approximation adc is used to attain a conver- sion time of 2 microseconds. start of conversion is initiated by cs and rd . following a start command the busy signal will become active and another start command should not be given until the conversion is complete. the reset ( rs ) input does not affect a/d conversion, but the int (interrupt or conversion complete) which normally goes active low at the end of a conversion will be forced high by reset asynchronously. figure 4 shows the wave forms for a conversion cycle. the track and hold begins holding the input voltage v in approximately 50 ns after the falling edge of the start command. the msb de- cision is made approximately 50 ns after the second falling edge of the clk. if t x is greater than 50 ns, then the falling edge of the clk will be seen as the first falling clock edge. if t x is less than 50 ns, the first msb conversion will not occur until one clock cycle later. the following bits will each be converted in a similar manner 50 ns after each clk edge until all eight bits have been converted. after the end of conversion the contents of the adc sar register are transferred to the output data latch, the track and hold is returned to the track mode, int goes low and the sar is reset. v in clk busy cs , rd or st 100ns typ 50ns typ msb decision db7 lsb decision db0 t x 50ns typ figure 4. operating waveforms using the external clock analog input the analog inputs of the ad8401 are fed into resistor voltage divider networks with a typical value of 8.5 k w . the amplifiers driving these inputs must have an output resistance low enough to drive these nodes without losing accuracy. taps from the voltage dividers are connected to the track and hold amplifier by the multiplexer switches. t/h v in d v in a 5k w mux agadc 5k w 3.57k w 3.57k w figure 5. equivalent analog input circuit track-and-hold amplifier following the resistive divider at the input of the ad8401 is a track-and-hold amplifier that captures input signals accurately up to the 200 khz nyquist frequency of the adc. to attain this performance the t/h amplifier must have a much greater band- width than the signal of interest. because of this the user must be careful to band limit the input signal to avoid aliasing high frequency components and noise into the passband. the track-and-hold amplifier is internally controlled by the start command and is not directly available to the user. after the start command signal the track-and-hold is placed into the hold mode; it returns to the track mode after the conversion is complete.
ad8401 C7C rev. 0 busy t 10 int t 16 t 15 cs t 14 t 8 t 17 rd data new data high z old data t 12 t 11 t 9 t 13 figure 7. mode 2, adc interface timing mode 2 interface this interface mode can be used with microprocessors that can be put into a wait state for at least 2 microseconds. the st pin must be tied to logic high for proper operation. the micro- processor begins a conversion by executing a read instruction that asserts the cs and rd pins at the ad8401s decoded ad- dress. the ad8401 busy output then goes low, forcing the microprocessors ready (or wait) line into a wait state. the analog input signal is captured by the t/h on the falling edge of rd . when the conversion is complete (8 clocks later), the busy line returns high, and then the m p completes its read of the new data now on the digital output port of the ad8401. note that while conversion is in progress the adc places the results from the last conversion (old data) on the data bus. the figure 7 timing diagram details the applicable timing specification requirements. digital interface: dac timing and control table ii shows the truth table for dac operation. the internal 8-bit dac register contents are loaded from the data bus when both wr and cs are asserted. the dac register determines the d/a converter analog-output voltage. the wr input is a posi- tive edge triggered input that loads the bus data into the dac register subject to the data setup and data hold timing require- ments. when cs and wr are low, the dac register contents will not change with changing data bus values. figure 8 provides the detail timing diagram for write cycle operation. table ii. dac register logic cs wr rs dac function h h h no effect l l h no effect l ` h dac register updated ` l h dac register updated x x l dac register loaded with all zeros t 2 cs t 5 wr data valid data t 3 t 1 t 4 figure 8. write cycle timing clock the ad8401 uses an external clock that is ttl or 5 v cmos compatible. the external clock speed is 5 mhz and the duty cycle may vary from 30% to 70%. the external clock can be continuously operated between conversions. digital interface: adc timing and control two basic adc operating modes are available with the ad8401. the first mode uses the start ( st ) pin to trigger a synchronized a/d conversion. as soon as the st pin is asserted, the t/h switches from tracking to the hold mode capturing the present analog input-voltage sample. with the t/h holding the analog sample the successive-approximation analog-to-digital conversion is completed on that sample value. at the end of conversion the t/h returns to the tracking mode. this mode of conversion is ideal for digital signal processing applications where precise interval sampling is necessary to minimize errors due to sampling uncertainty or jitter. a precise clock source can be used to drive the st input. the second mode of conversion is started by the rd and cs in- puts going low, after which the busy line puts the micropro- cessor into a wait state until end of conversion. mode 2 is asserted by connecting the st pin to logic high. the major ad- vantage of this interface is that a single read instruction will start and complete a new analog-to-digital conversion without the need for carefully tailored software delays that often are not portable when software routines are taken to a different proces- sor running at a different clock speed. busy st t 6 t 7 t convert t 8 int t 9 t 15 t 12 cs t 14 t 11 t 10 t 13 rd data data valid high z figure 6. mode 1, adc interface timing mode 1 interface as shown in figure 6, the falling edge of the st pulse initiates a conversion and puts the t/h amplifier into the hold mode. the busy signal goes low during the whole a/d conversion time and returns high signaling end of conversion. the int line can be used to interrupt the microprocessor. when the microproces- sor performs a read to access the ad8401 data, the rising edges of cs or rd will reset the int output to high after the t 15 timing specification. int can also be used to externally trigger a pulse that activates the cs and rd and places the new data into a buffer or first in first out fifo memory. the microproces- sor can then load a series of readings from this buffer memory at a convenient time. care must be taken not to have the st input high when rd is brought low; otherwise, the ad8401 will not operate properly. also triggering the st line a second time be- fore conversion is complete will cause erroneous readings.
ad8401 C8C rev. 0 an active low pulse, at any time, on the reset pin asynchro- nously forces all dac register bits to zero. the dac output voltage becomes zero volts and stays at that value until a new data word is loaded into the dac register with a new wr com- mand. the equivalent input logic for the dac register loading is shown in figure 9. reset cs wr dac register d0 d7 input data to dac ladder figure 9. equivalent dac register control logic typical performance characteristics 1.0 ?.1 256 ?.5 0 0 0.5 192 128 64 digital input code ?decimal v dd = +5v t a = +25 c linearity error ?lsb figure 10. adc linearity error vs. digital code 1.0 ?.1 256 ?.5 0 0 0.5 192 128 64 digital input code ?decimal v dd = +5v t a = +25 c linearity error ?lsb figure 11. dac linearity error vs. digital code 120 0 4.5 30 10 ?.5 20 ?.5 60 40 50 70 80 90 110 100 3.5 2.5 1.5 0.5 ?.5 ?.5 ?.5 full scale error ?lsb units ss = 300 units t a = +25 c figure 12. adc full-scale error histogram 2.5 ?.0 ?.5 ?.5 ?.0 0 ?.0 ?.5 0.5 1.0 1.5 2.0 100 ?5 ?0 75 50 25 0 temperature ? c adc full-scale error ?lsb v dd = +5v figure 13. adc full-scale error vs. temperature
ad8401 C9C rev. 0 t a = +25 c ss = 300 units ? ? 4 3 2 1 0 ? ? full scale error ?lsb 0 240 60 20 40 120 80 100 140 160 180 220 200 units figure 14. dac full-scale error histogram 3.0 ?.5 ?.0 ?.0 ?.5 0.5 ?.5 0 1.0 1.5 2.0 2.5 dac full scale error ?lsb 100 ?5 ?0 75 50 25 0 temperature ? c v dd = +5v x +3 s x ?3 s x figure 15. dac full-scale error vs. temperature 500 100 0 400 300 200 burn-in time @ 150 c ?hours 4 ? ? ? ? ? 0 1 2 3 dac full scale out change ?lsb v dd = +5v ss = 135 units x ?3 s x x +3 s figure 16. dac full-scale out change vs time accelerated by burn-in v dd = +5v t a = +25 c r l to v dd r l to gnd 100 10k 1k 100k 10 load resistance ? w 2.5 1.0 0 0.5 1.5 2.0 output voltage ?volts figure 17. dac output swing vs. load resistance 10 90 100 0% 1v 5v 1 m s 5v 3 2 1 0 5v 0 5v 0 5v 0 v out data wr time ?1 m s/div figure 18. dac output slew rate positive transition 10 90 100 0% 1v 5v 1 m s 5v 3 2 1 0 5v 0 0 5v 0 v out data wr time ?1 m s/div figure 19. dac output slew rate negative transition
ad8401 C10C rev. 0 100 ?5 ?0 75 50 25 0 temperature ? c 10.0 6.0 7.0 6.5 8.0 7.5 8.5 9.0 9.5 supply current ?ma v in = +2.4v v dd = +5.25v v dd = +4.75v figure 21. supply current vs. temperature 10 90 100 0% 500mv 20 m s time ?20 m s /div v dd = +5v t a = +25 c c l = 1000pf v out ?0.5v /div figure 20. dac output swing with capacitive load 1k 10k 1m 100k frequency ?hz 20 0 40 60 power supply rejection ?db t a = +25 c output = full scale v dd = 5v 200mv figure 22. power supply rejection ratio vs. frequency
ad8401 C11C rev. 0 table iii. dac unipolar code nominal analog dac register contents general transfer decimal binary equation output v out 255 1111 1111 2 . 500 255 256 2.490 v 129 1000 0001 2 . 500 129 256 1.260 v 128 1000 0000 2 . 500 128 256 1.250 v 127 0111 1111 2 . 500 127 256 1.240 v 1 0000 0001 2 . 500 1 256 0.010 v 0 0000 0000 2 . 500 0 256 0.000 v applications information the software programming needs to format data as defined by the transfer equations and code tables that follow. dac transfer equation v out = 2.500 d 256 = 2.500 255 256 for a 2.50 v full scale where d is the decimal value 0 through 255 of the 8-bit data word. the nominal output voltages listed in the code table are sub- ject to the static performance specifications. the inl, zero- scale and full-scale errors describe the total specified variation that will be encountered from part to part. one lsb of error for the 2.5 v fs range is 9.766 millivolts (= 2.50/256). although separate agnds exist for both the dac and adc to minimize crosstalk, writing data to the dac while the adc is performing a conversion may result in an incorrect conversion from the adc due to signal interaction between the dac and adc. therefore, to ensure correct operation of the adc, the dac register should not be updated while the adc is converting. the ad8401 is configured for an input range of +3.0 volts full scale. the nominal transfer characteristic for this range is plot- ted in figure 23. the output coding is natural binary with one lsb equal to 11.72 millivolts. note that the first code transition between 0 lsb and 1 lsb occurs at 5.8 mv, one half of the 11.72 mv lsb step size. the last code transition occurs at full scale minus 1.5 lsbs, which is a 2.982 v input. the ad8401 is easily interfaced to most microprocessors by us- ing either address bits or address decode to select the appropri- ate multiplexer channel. figure 24 shows how easily the ad8401 interfaces to the ad899. no additional hardware is required. output code full scale transition 123 fs fs ?1lsb v in input voltage ?lsbs 1lsb = fs 256 11111111 11111110 11111101 00000011 00000010 00000001 00000000 figure 23. adc 0 v to +3 v input transfer characteristic
ad8401 C12C rev. 0 c1857C18C10/93 printed in u.s.a. 28-lead wide-body so (sol-28) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 28 15 14 1 outline dimensions dimensions shown in inches and (mm). v dd (+5.0v) 1.25v ref 8-bit dac v out control logic dac reg adc reg 8-bit adc address bus t/h ad899 a b c d a1 a0 ag adc ag dac data i/o (8 bits) a0 a1 v in a v in b v in c v in d dgnd reset int busy st clock wr cs rd ad8401 figure 24. ad8401 interface to the ad899 read-channel hard disk drive circuit

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